The disclosed subject matter relates generally to computing systems and, more particularly, to a method and apparatus for reducing simultaneous switching outputs using data bus inversion signaling.
In computing systems, dynamic memory devices are used to store large amounts of data for use by a processor or other computing device during its operation. Data is transferred between the computing device and the memory device over a memory bus. In such electronic systems, it is common that different power requirements exist for driving an electrical “1” versus driving an electrical “0”. For example, in some double data rate (DDR) synchronous dynamic random access memory (SDRAM), more power is consumed driving a “0” than a “1”.
Data bus inversion (DBI) is an I/O signaling technique that aims to reduce DC power consumption by selectively inverting the data bus for systems where the power consumed between alternate signaled states is asymmetric. The device communicating the data (i.e., the processor for a write operation or the memory device for a read operation) counts the number of 0s driven on a bus during a bit transfer time, and if more than half the bus is electrical 0, the bus state is inverted. A DBI indicator bit is toggled to indicate that bus inversion has occurred. If the number of 0s and 1s in the bit transfer time are less than or equal to half the bus width, no inversion takes place. When the receiving device processes the data, the DBI indicator bit is used as a trigger to invert the data again to reconstitute the original data pattern. In this manner, the average number of 1s transmitted in a bit transfer time is increased, thereby reducing DC power. Bus inversion may also be used in the case of address lines. Hence, as used herein the term data bus inversion applies generically to any type of bus inversion, such as DQ buses or address buses.
DBI also has the property of reducing simultaneous switching outputs (SSO), defined as the absolute value of the number outputs that change to 1 minus the number of outputs that change to 0 in two consecutive bit time transfers. In a system where transmitting 1s is lower power than transmitting 0s, the transmitted DBI bit is defined as 1 for no inversion and 0 for inversion. If all bit transfer times require inversion (e.g., a stream of 0s, which would be inverted to 1s), and the DBI vector is transmitted after the last data transfer time, the system sees a worst case SSO transition where the last data transfer is all 1s and the DBI bit transfer is all 0s. Thus, DBI can introduce new SSO problems and reduce the overall SSO benefit.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.